<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Cuda on icyveins7's blog</title><link>https://icyveins7.github.io/tags/cuda/</link><description>Recent content in Cuda on icyveins7's blog</description><generator>Hugo</generator><language>en-us</language><copyright>This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.</copyright><lastBuildDate>Wed, 02 Sep 2026 20:00:00 +0800</lastBuildDate><atom:link href="https://icyveins7.github.io/tags/cuda/index.xml" rel="self" type="application/rss+xml"/><item><title>Large pinned host allocations in CUDA</title><link>https://icyveins7.github.io/posts/2026/09/large-pinned-host-allocations-in-cuda/</link><pubDate>Wed, 02 Sep 2026 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2026/09/large-pinned-host-allocations-in-cuda/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;Sometimes, you just can&amp;rsquo;t fit everything in VRAM.&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;In most CUDA projects, the advice is usually to transfer all inputs, outputs, and temporary scratch space to the device. Working completely inside VRAM is &lt;em&gt;fast&lt;/em&gt;, and avoids both the complexity and the throughput hit that comes with over-PCIe transfers being scattered throughout your hot path.&lt;/p&gt;&#10;&lt;p&gt;All of this is correct, and I adhere to this myself as much as possible. Sometimes, though, you simply just can&amp;rsquo;t do this, and recently I was left with no choice and had to start migrating stuff back to host memory.&lt;/p&gt;</description></item><item><title>Occupancy-maxxing is just Starcraft</title><link>https://icyveins7.github.io/posts/2026/08/occupancy-maxxing-is-just-starcraft/</link><pubDate>Wed, 12 Aug 2026 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2026/08/occupancy-maxxing-is-just-starcraft/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;If you can manage minerals and gas, you can manage CUDA threads and registers.&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;blockquote&gt;&#10;&lt;p&gt;CUDA is just resource management.&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;Okay, of course there&amp;rsquo;s a lot more to squeezing CUDA kernel performance than &lt;em&gt;just resource management&lt;/em&gt;, but occupancy is very often the simplest thing to strive for, once you know how. And usually, if you&amp;rsquo;ve hit 100% occupancy, then unless you&amp;rsquo;ve done something heinous in your code, further optimizations are unlikely to budge your performance by large factors (aside from an entire algorithmic shift, but we won&amp;rsquo;t discuss that here).&lt;/p&gt;</description></item><item><title>Your left-right boundary search is actually a CUDA-friendly single scan</title><link>https://icyveins7.github.io/posts/2026/06/your-left-right-boundary-search-is-actually-a-cuda-friendly-single-scan/</link><pubDate>Fri, 26 Jun 2026 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2026/06/your-left-right-boundary-search-is-actually-a-cuda-friendly-single-scan/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;At least, most of the time it is. As long as it fits the 1-2-1 pattern..&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;Many segments can be boiled down to what I call a 1-2-1 pattern. For an array of input elements (I&amp;rsquo;ll just call them pixels, it&amp;rsquo;s shorter for me to type), a naive segment detection is to loop forwards until you hit an &lt;em&gt;activation&lt;/em&gt; pixel. This can internally be any condition you&amp;rsquo;d like; that is, any &lt;code&gt;if (...)&lt;/code&gt; is possible here as long as you operate only on the pixel you&amp;rsquo;re currently at. For simplicity, I&amp;rsquo;ll assume this is the &lt;code&gt;2&lt;/code&gt; pixel:&lt;/p&gt;</description></item><item><title>Avoid being baited by your printf statements in CUDA kernels</title><link>https://icyveins7.github.io/posts/2026/03/avoid-being-baited-by-your-printf-statements-in-cuda-kernels/</link><pubDate>Mon, 23 Mar 2026 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2026/03/avoid-being-baited-by-your-printf-statements-in-cuda-kernels/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;Behaviour of printf on device is not the same as on host!&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;If you&amp;rsquo;re a &lt;code&gt;printf&lt;/code&gt; aficionado like me, then you use &lt;code&gt;printf&lt;/code&gt; for debugging. A lot. In fact I previously wrote a small logger that uses &lt;code&gt;printf&lt;/code&gt; called &lt;a href="https://github.com/icyveins7/spfLogger"&gt;spfLogger&lt;/a&gt;. I do enjoy the flexibility of tuning every single width/precision with a few characters, and it&amp;rsquo;s something I haven&amp;rsquo;t yet seen C++ be able to emulate with as little irritation.&lt;/p&gt;&#10;&lt;blockquote&gt;&#10;&lt;p&gt;I haven&amp;rsquo;t gotten around to writing code using newer &lt;code&gt;std::format&lt;/code&gt; or &lt;code&gt;println&lt;/code&gt; yet, so the jury&amp;rsquo;s out on that.&lt;/p&gt;</description></item><item><title>Iterative algorithms with CUDA</title><link>https://icyveins7.github.io/posts/2025/11/iterative-algorithms-with-cuda/</link><pubDate>Sat, 29 Nov 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/11/iterative-algorithms-with-cuda/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;Because not everything can be made un-iterative..&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;There&amp;rsquo;s a pretty large class of algorithms that have been developed for CPUs that involve, optimally, an iterative solver.&lt;/p&gt;&#10;&lt;p&gt;Usually, this is defined by some notion of &lt;em&gt;convergence&lt;/em&gt;; some variable is updated, and then at the end of each iteration it is checked to determine whether further iterations are required.&lt;/p&gt;&#10;&lt;p&gt;This is all fine and dandy in CPU-land, but in GPUs this almost always makes the flow awkward.&lt;/p&gt;</description></item><item><title>Some tips for integrating small bits of CUDA code into larger codebases</title><link>https://icyveins7.github.io/posts/2025/08/some-tips-for-integrating-small-bits-of-cuda-code-into-larger-codebases/</link><pubDate>Wed, 13 Aug 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/08/some-tips-for-integrating-small-bits-of-cuda-code-into-larger-codebases/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;Some lessons from general C++ come in handy here..&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;In some recent work I integrated some CUDA code I developed into a larger existing codebase, written for the CPU. Essentially, my module(s) would accelerate and replace some existing functionality, but was only a small cog in the machine.&lt;/p&gt;&#10;&lt;p&gt;This is likely applicable to many others, so hopefully the lessons I document here will be concisely useful to those who chance upon this post.&lt;/p&gt;</description></item><item><title>Quickly sketching out a BlockQuickSelect</title><link>https://icyveins7.github.io/posts/2025/07/quickly-sketching-out-a-blockquickselect/</link><pubDate>Sun, 20 Jul 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/07/quickly-sketching-out-a-blockquickselect/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;I wrote a blockwide quickselect. That&amp;rsquo;s the post.&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;As of today, NVIDIA&amp;rsquo;s &lt;code&gt;cub&lt;/code&gt; library has a few block-wide primitives to do sorting - like &lt;code&gt;BlockRadixSort&lt;/code&gt; - but none that do the equivalent for the $k$&amp;lsquo;th order statistic i.e the $k$-th smallest element.&lt;/p&gt;&#10;&lt;p&gt;This would be functionally equivalent to the CPU&amp;rsquo;s &lt;code&gt;std::nth_element&lt;/code&gt;, but that &lt;a href="https://en.cppreference.com/w/cpp/algorithm/nth_element.html"&gt;apparently uses Introselect&lt;/a&gt;, which is a tad too much for me to want to implement. I&amp;rsquo;m going to stick with the simpler &lt;a href="https://en.m.wikipedia.org/wiki/Quickselect"&gt;quickselect&lt;/a&gt;.&lt;/p&gt;</description></item><item><title>Interesting Tidbits from GTC 2025: CUDA Graphs</title><link>https://icyveins7.github.io/posts/2025/03/interesting-tidbits-from-gtc-2025-cuda-graphs/</link><pubDate>Tue, 25 Mar 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/03/interesting-tidbits-from-gtc-2025-cuda-graphs/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;In the 2nd post of this series, I give a short introduction on something that is also not particularly new, but new to me - CUDA Graphs!&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;As stated in my first post of this series, this topic isn&amp;rsquo;t particularly new per-se. Indeed, it looks like it has been out since 2019. But maybe CUDA graphs have increased in relevance now that GPUs are more powerful. As usual, a good starting reference is NVIDIA&amp;rsquo;s own &lt;a href="https://developer.nvidia.com/blog/cuda-graphs/"&gt;blogpost&lt;/a&gt;.&lt;/p&gt;</description></item><item><title>Interesting Tidbits from GTC 2025: Asynchronicity Beyond Streams</title><link>https://icyveins7.github.io/posts/2025/03/interesting-tidbits-from-gtc-2025-asynchronicity-beyond-streams/</link><pubDate>Mon, 24 Mar 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/03/interesting-tidbits-from-gtc-2025-asynchronicity-beyond-streams/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;Some notes for CUDA programmers who haven&amp;rsquo;t kept up with the times; this first post covers in-kernel pipelining..&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;I recently had the privilege of being sponsored to attend the March 2025 GTC in person. While the sessions were very largely dominated by AI-related things, I generally selected the CUDA-related ones, since they were more relevant to my work (and interests).&lt;/p&gt;&#10;&lt;p&gt;I&amp;rsquo;ll try to encapsulate some of the new things I learnt while I was there into a few major concepts. Note that most, if not all of these, are not shiny new CUDA features - some of them have been out for several years, but I just didn&amp;rsquo;t know about them, so I learnt about them there.&lt;/p&gt;</description></item><item><title>AtomicMinFloat; overloading integer-only atomics for floating-point numbers in CUDA</title><link>https://icyveins7.github.io/posts/2025/03/atomicminfloat-overloading-integer-only-atomics-for-floating-point-numbers-in-cuda/</link><pubDate>Sun, 16 Mar 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/03/atomicminfloat-overloading-integer-only-atomics-for-floating-point-numbers-in-cuda/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;Convincing you (and myself) that with some minor edits, we can still use atomicMin for floats in CUDA..&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;CUDA has a set of atomic functions for &lt;em&gt;safely&lt;/em&gt; updating the same memory address with different threads. There&amp;rsquo;s a whole list of them in the programming guide &lt;a href="https://docs.nvidia.com/cuda/cuda-c-programming-guide/#atomic-functions"&gt;here&lt;/a&gt;.&lt;/p&gt;&#10;&lt;p&gt;However, for &lt;code&gt;atomicMin&lt;/code&gt; (and also &lt;code&gt;atomicMax&lt;/code&gt;), there isn&amp;rsquo;t an overload that works with &lt;code&gt;float&lt;/code&gt;s (or &lt;code&gt;double&lt;/code&gt;s , but who uses those in CUDA anyway..). For this discussion we&amp;rsquo;ll just focus on &lt;code&gt;atomicMin&lt;/code&gt;, but all the points we discuss can be inverted to explain &lt;code&gt;atomicMax&lt;/code&gt;.&lt;/p&gt;</description></item><item><title>Gotta go (randomly) fast, thrust vs cuRAND</title><link>https://icyveins7.github.io/posts/2025/03/gotta-go-randomly-fast-thrust-vs-curand/</link><pubDate>Mon, 10 Mar 2025 20:00:00 +0800</pubDate><guid>https://icyveins7.github.io/posts/2025/03/gotta-go-randomly-fast-thrust-vs-curand/</guid><description>&lt;blockquote&gt;&#10;&lt;p&gt;How fast can you generate (pseudo-)random numbers on the GPU?&#10;How fast can you generate (pseudo-)random numbers on the GPU?&lt;/p&gt;&#10;&lt;/blockquote&gt;&#10;&lt;p&gt;I recently had to answer this question. Well, not exactly this question, but this was a key part of it.&lt;/p&gt;&#10;&lt;p&gt;A quick google search will bring up two common methods (libraries) when trying to do this in CUDA: thrust and cuRAND. Thrust is known to be a lot easier to set up; no need to write the kernel code and nitty gritty details, so I started with that.&lt;/p&gt;</description></item></channel></rss>